- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360777 > ICS9147F-01 Frequency Generator & Integrated Buffers for PENTIUMTM PDF資料下載
參數(shù)資料
| 型號： | ICS9147F-01 |
| 英文描述： | Frequency Generator & Integrated Buffers for PENTIUMTM |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 442K |
| 代理商： | ICS9147F-01 |
5
ICS9147-01
Notes:
1. All timing is referenced to the Internal CPU clock (defined as inside the ICS9147 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9147.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal is synchronized internal by the
ICS9147-01
prior to its control
action of powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal
clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to
a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be
less than 3mS. The power down latency is less than three CPU clock cycles. BUSSTOP# and CPUSTOP# are don’t care
signals during the power down operations.
PD# Timing Diagram
Notes:
1. All timing is referenced to the Internal BUS clock (defined as inside the ICS9147 device.)
2. BUSSTOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be
synchronized inside the ICS9147.
3. All other clocks continue to run undisturbed.
4. PD# and CPUSTOP# are shown in a high (true) state.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS9147-09 | Frequency Generator & Integrated Buffers for 686 Series CPUs |
| ICS9147-12 | Low-Power High-Performance Impact<TM> PAL<R> Circuits 24-PDIP 0 to 75 |
| ICS9147-14 | High-Performance Impact-X<TM> PAL<R> Circuits 28-PLCC 0 to 75 |
| ICS9147-16 | High-Performance Impact-X<TM> PAL<R> Circuits 24-PDIP 0 to 75 |
| ICS9147-22 | High-Performance Impact-X<TM> PAL(R) Circuits 28-PLCC 0 to 75 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9147F-03 | 制造商:INT_CIR_SYS 功能描述: |
| ICS9147F-06 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
| ICS9147F-06T | 制造商:ICS 功能描述: |
| ICS9147F-08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ICS9147F-08T | 制造商:ICS 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。