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參數(shù)資料
| 型號： | ICS9150F-04 |
| 英文描述： | Pentium Pro⑩ and SDRAM Frequency Generator |
| 中文描述： | 奔騰Pro⑩和SDRAM頻率發(fā)生器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 329K |
| 代理商： | ICS9150F-04 |
4
ICS9150-01
VDD(1,2,3)
This is the power supply to the internal core logic of the device as well
as the clock output buffers for REF(0:1), PCICLK, and
SDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed buffers that it
supplies will have a voltage swing from Ground to this level. For the
actual guaranteed high and low voltage levels for the Clocks, please
consult the DC parameter table in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers that each supplies will have a voltage swing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
GND
This is the power supply ground (common or negative) return pin for
the internal core logic and all the output buffers.
X1
This input pin serves one of two functions. When the device is used
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. This pin also implements an internal Crystal loading capacitor
that is connected to ground. See the data tables for the value of this
capacitor.
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
output signal that drives (or excites) the discrete Crystal. The X2 pin
will also implement an internal Crystal loading capacitor that is
connected to ground. See the Data Sheet for the value of this
capacitor.
CPUCLK (0:4)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
Clocks are controlled by the Voltage level applied to the VDDL2 pin
of the device. See the Functionality Table for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
SDRAM(0:15)
These Output Clocks are use to drive Dynamic RAM’s and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAM’s output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.
IOAPIC (0:2)
These Outputs are fixed frequency Output Clocks that run at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
Technical Pin Function Descriptions
REF0
The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically
14.31818MHz) attached across X1 and X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification. They run at 1/2 CPU frequency.
FS0
This Input pin controls the frequency of the Clocks at the CPU,
PCICLK and SDRAM output pins. If a logic “1” value is present on
this pin, the 66.6 MHz Clock will be selected. If a logic “0” is used,
the 60MHz frequency will be selected. (This is the Power Management
Mode)
MODE
This Input pin is used to select the Input function of the I/O pins.
An active Low will place the I/O pins in the Input mode and enable
those stop clock functions. (This is the Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the CPUCLK
clocks in an active low state. All other Clocks including SDRAM
clocks will continue to run while this function is enabled. The
CPUCLK’s will have a turn ON latency of at least 3 CPU clocks. This
input pin only valid when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the PCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
Management Mode)
I
2
C
The SDATA and SCLOCK Inputs are use to program the device. The
clock generator is a slave-receiver device in the I
2
C protocol. It will
allow read-back of the registers. See configuration map for register
functions. The I
2
C specification in Philips I
2
C Peripherals Data
Handbook (1996) should be followed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9150F-08 | Frequency Generator & Integrated Buffers for Pentium/Pro⑩ |
| ICS9150-01 | Pentium Pro⑩ and SDRAM Frequency Generator |
| ICS9150-02 | Pentium Pro™ and SDRAM Frequency Generator |
| ICS9150-04 | Pentium Pro⑩ and SDRAM Frequency Generator |
| ICS9150-08 | Frequency Generator & Integrated Buffers for Pentium/Pro⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9150F04T | 制造商:ICS 功能描述:New |
| ICS9150F-08 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Pentium/Pro⑩ |
| ICS9150F-11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ICS9154A-27CS16 | 功能描述:IC FREQUENCY GENERATOR 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS9154A-27CS16LF | 功能描述:IC FREQUENCY GENERATOR 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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