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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ICS91857AG
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 2/14闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CLOCK DRIVER SSTL_2 48-TSSOP
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Product Discontinuation 09/Dec/2011
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 39
椤炲瀷锛� 鏅傞悩椹�(q奴)鍕曞櫒
PLL锛� 甯舵梺璺�
杓稿叆锛� LVCMOS
杓稿嚭锛� SSTL-2
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 1:10
宸垎 - 杓稿叆:杓稿嚭锛� 鐒�/鏄�
闋荤巼 - 鏈€澶э細 230MHz
闄ゆ硶鍣�/涔樻硶鍣細 鐒�/鐒�
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-TFSOP锛�0.240"锛�6.10mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-TSSOP
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� 91857AG
10
ICS91857
0494C鈥�08/15/05
(N is a large number of samples)
t( ) n+1
t() n
t()=
1
n=N
t() n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t(SK_O)
Y #
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
YX
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output Skew
1
fO
t
= t
-
(jit_per)
C(n)
1
fO
Figure 6. Period Jitter
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ICS91857AGLF 鍔熻兘鎻忚堪:IC CLOCK DRIVER SSTL_2 48-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷堟檪 - 鏅傞悩鐧�(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,000 绯诲垪:- 椤炲瀷:PLL 鏅傞悩鐧�(f膩)鐢熷櫒 PLL:甯舵梺璺� 杓稿叆:LVCMOS锛孡VPECL 杓稿嚭:LVCMOS 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:2:11 宸垎 - 杓稿叆:杓稿嚭:鏄�/鐒� 闋荤巼 - 鏈€澶�:240MHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:3.135 V ~ 3.465 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:32-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-TQFP锛�7x7锛� 鍖呰:甯跺嵎 (TR)
ICS91857AGLFT 鍔熻兘鎻忚堪:IC CLOCK DRIVER SSTL_2 48-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷堟檪 - 鏅傞悩鐧�(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,000 绯诲垪:- 椤炲瀷:PLL 鏅傞悩鐧�(f膩)鐢熷櫒 PLL:甯舵梺璺� 杓稿叆:LVCMOS锛孡VPECL 杓稿嚭:LVCMOS 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:2:11 宸垎 - 杓稿叆:杓稿嚭:鏄�/鐒� 闋荤巼 - 鏈€澶�:240MHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:3.135 V ~ 3.465 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:32-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-TQFP锛�7x7锛� 鍖呰:甯跺嵎 (TR)
ICS91857AGT 鍔熻兘鎻忚堪:IC CLOCK DRIVER SSTL_2 48-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷堟檪 - 鏅傞悩鐧�(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Product Discontinuation 04/May/2011 妯�(bi膩o)婧�(zh菙n)鍖呰:96 绯诲垪:- 椤炲瀷:鏅傞悩鍊嶉牷鍣紝闆跺欢閬茬珐娌栧櫒 PLL:甯舵梺璺� 杓稿叆:LVTTL 杓稿嚭:LVTTL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1:8 宸垎 - 杓稿叆:杓稿嚭:鐒�/鐒� 闋荤巼 - 鏈€澶�:133.3MHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:3 V ~ 3.6 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-TSSOP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:23S08-5HPGG
ICS91857YGLFT-LF-T 鍒堕€犲晢:ICS 鍒堕€犲晢鍏ㄧū:ICS 鍔熻兘鎻忚堪:Value SSTL_2 Clock Driver (60MHz - 220MHz)
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*鍨嬭櫉 *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉 灏佽
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鎴戠殑鑱�(li谩n)绯绘柟寮�

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