參數(shù)資料
型號(hào): ICS932S431AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 19/22頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK CHIP 56-TSSOP
標(biāo)準(zhǔn)包裝: 34
類型: 時(shí)鐘/頻率合成器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
其它名稱: 932S431AGLF
6
Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
1426A—11/12/09
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Current Source Output
Impedance
Zo
VO = Vx
3000
1
Voltage High
VHigh
660
850
mV
1,3
Voltage Low
VLow
-150
150
mV
1,3
Max VoltageVovs
1150
mV
1
Min Voltage
Vuds
-300
mV
1
Crossing Voltage (abs)
Vx(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vx
Variation of crossing over all
edges
140
mV
1
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
525
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
525
ps
1
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
125
ps
1
Fall Time Variation
d-tf
VOH = 0.525V VOL = 0.175V
125
ps
1
Long Term Jitter
tjLT
Measurement from differential
wavefrom @ 10 us
0300
500
ps
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
Skew
tsk3
VT = 50%
250
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
125
ps
1
*T
A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, IREF = 475
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3I
REF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Statistical measurement on
single ended signal
Measurement on single ended
signal using absolute value.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
VO = Vx
3000
1
Voltage High
VHigh
660
850
mV
1,3
Voltage Low
VLow
-150
150
mV
1,3
Max Voltage
Vovs
1150
mV
1
Min Voltage
Vuds
-300
mV
1
Crossing Voltage (abs)
Vx(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vx
Variation of crossing over all
edges
140
mV
1
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
525
ps
1
Fall Time
tf
VOL = 0.175V, VOH = 0.525V
175
525
ps
1
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
125
ps
1
Fall Time Variation
d-tf
VOL = 0.175V, VOH = 0.525V
125
ps
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
Skew
tsk3
across all CPU outputs,
VT = 50%
50
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
50
ps
1
*T
A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, IREF = 475
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3I
REF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Statistical measurement on
single ended signal
Measurement on single ended
signal using absolute value.
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