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參數(shù)資料
| 型號(hào)： | ICS93701 |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復(fù)員鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 9/9頁 |
| 文件大?。?/td> | 184K |
| 代理商： | ICS93701 |
9
ICS93701
0417B—10/29/02
Ordering Information
ICS93701
y
GT
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator
(will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX
y
G PPP - T
AREA
INDEX
1 2
N
D
E1
E
PLANE
SEATING
A1
A
A2
e
- C -
b
c
L
aaa
C
MIN
--
0.05
0.80
0.17
0.09
SEE VARIATIONS
8.10 BASIC
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.319 BASIC
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
6.00
6.20
.236
.244
0.45
SEE VARIATIONS
0.75
.018
SEE VARIATIONS
.030
0°
--
8°
0°
--
8°
0.10
.004
VARIATIONS
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
48
10-0039
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
SYMBOL
In Inches
0.50 BASIC
0.020 BASIC
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS93701YGT | DDR Phase Lock Loop Clock Driver |
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS93701YGT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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