- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360784 > ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS93705 |
| 英文描述： | DDR Phase Lock Loop Zero Delay Clock Buffer |
| 中文描述： | 復(fù)員鎖相環(huán)零延遲時(shí)鐘緩沖器 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 65K |
| 代理商： | ICS93705 |
5
ICS93705
0418C—08/08 /02
Timing Requirements
T
A
= 0 - 70C; Supply Voltage AV
DD
, V
DD
= 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
Operating Clock Frequency
1
freq
op
Input Clock Duty Cycle
1
d
tin
Clock Stabilization
1
t
STAB
CONDITIONS
MIN
TYP
MAX
UNITS
66
170
MHz
40
60
%
μ
s
from V
DD
= 2.5V to 1% target frequency
100
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
T
A
= 0 - 70C; Supply Voltage V
DD
= 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
66 MHz
120
100 / 125 / 133 / 167 MHz
75
66 MHz
50
110
100 / 125 / 133 / 167 MHz
35
65
Phase Error
1
Output to output Skew
1
t
pe
with input clock 0-2.5V 0.8ns rise/fall
-150
50
150
ps
T
skew
with input clock 0-2.5V 0.8ns rise/fall
40
100
ps
Low-to-high level Propagation
Delay Time, Bypass Mode
1
t
PLH
CLK_IN to any output, Load = 120W / 12 pF
4
4.5
6
ns
Pulse Skew
1
T
skewp
D
C
t
R
, t
F
100
ps
Duty Cycle (differential)
1,3
Rise Time, Fall Time
1
no loads, 66 MHz to 167 MHz
Single-ended 20 - 80 %; Load = 120
/ 12 pF
49
50
51
%
450
550
950
ps
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = t
wH
/ t
C
, where the cycle time (t
C
) decreases as the frequency increases.
ps
ps
Absolute Jitter
1
Cycle to cycle Jitter
1,2
t
jabs
t
c-c
Recommended Operating Condition
T
A
= 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Analog/core supply
voltage
V
IL
V
IH
Input duty cycle
I
DC
Input max jitter
I
TCYC
MIN
TYP
MAX
UNITS
V
DD
, A
VDD
2.3
2.5
2.7
V
-
VDD/2 - 0.5V
-
60
500
V
V
%
ps
VDD/2 + 0.5V
40
Input voltage level
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
| ICS93712 | 2 DIMM DDR Fanout Buffer |
| ICS93716 | Low Cost DDR Phase Lock Loop Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93716 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Cost DDR Phase Lock Loop Clock Driver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。