參數(shù)資料
型號(hào): ICS93735
英文描述: DDR Phase Lock Loop Zero Delay Clock Buffer
中文描述: 復(fù)員鎖相環(huán)零延遲時(shí)鐘緩沖器
文件頁數(shù): 6/7頁
文件大?。?/td> 126K
代理商: ICS93735
6
ICS93735
0579E—08/06/03
Recommended Operation Conditions
T
A
= 0 - 70°C; Supply Voltage AV
DD
, V
DD
= 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
Analog / Core Supply Voltag
AV
DD
Input Voltage Level
V
IN
Output Differential Pair
Crossing Voltage
CONDITIONS
MIN
2.3
2
TYP
2.5
2.5
MAX
2.7
3
UNITS
V
V
1.32
V
V
OC
66/100/133/166MHz, V
DD
=2.50V
1.23
1.25
Timing Requirements
T
A
= 0 - 70°C; Supply Voltage AV
DD
, V
DD
= 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
Operating Clock Frequency
1
freq
op
Input Clock Duty Cycle
1
d
tin
Clock Stabilization
1
t
STAB
1. Guaranteed by design, not 100% tested in production.
CONDITIONS
MIN
22
40
TYP
MAX
340
60
100
UNITS
MHz
%
μ
s
Input Voltage level: 0-2.50V
50
from VDD = 2.5V to 1% target frequency
Switching Characteristics
T
A
= 0 - 70°C; Supply Voltage AV
DD
, V
DD
= 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
66 MHz
100 / 125 / 133 MHz
MIN
46
27
TYP
52
33
-113
MAX
63
40
UNITS
Phase Error
1
Output to output Skew
1
Low-to-high level Propagation
Delay Time, Bypass Mode
1
Pulse Skew
1
Duty Cycle (Sign Ended)
1,3
Rise Time
1
Fall Time
1
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formular: duty_cycle=t
wH
/t
C
, where the cycle time (t
C
)decreases as the frequency increases.
t
pe
T
skew
100MHz, input clock 0-2.5V, 0.8ns rise/fall
input clock 0-2.5V, 0.8ns rise/fall
CLK_IN to any output,
100MHz, Load = 120 W / 12 pF
ps
ps
66
98
T
skew
DC
t
R
t
F
ps
%
ps
ps
no loads, 66 MHz to 167MHz
Single-ended 20-80 %; Load=120W/12pF
Single-ended 20-80 %; Load=120W/12pF
50.2
400
435
51.3
622
711
490
579
Cycle to cycle Jitter
1,2
t
c-c
ps
t
PLH
3.67
3.68
ns
相關(guān)PDF資料
PDF描述
ICS93735F-T DDR Phase Lock Loop Zero Delay Clock Buffer
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