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參數(shù)資料
| 型號： | ICS950908BFLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 0K |
| 描述： | IC TIMING CTRL HUB P4 56-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TCH™ |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，Timing Control Hub? |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:18 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200.4MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 950908BFLFT |
4
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Pin Description Continued
PIN
#
NAME
TYPE
29
DDRC5/SDRAM11
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
30
DDRT5/SDRAM10
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
31
DDRC4/SDRAM9
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
32
DDRT4/SDRAM8
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
33
GND
PWR
Ground pin.
34
VDD3.3_2.5
PWR
2.5V or 3.3V nominal power supply voltage.
35
DDRC3/SDRAM7
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
36
DDRT3/SDRAM6
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
37
DDRC2/SDRAM5
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
38
DDRT2/SDRAM4
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
39
GND
PWR
Ground pin.
40
VDD3.3_2.5
PWR
2.5V or 3.3V nominal power supply voltage.
41
DDRC1/SDRAM3
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
42
DDRT1/SDRAM2
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
43
DDRC0/SDRAM1
OUT
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
44
DDRT0/SDRAM0
OUT
"True" Clock of differential memory output / 3.3V SDRAM clock output
45
BUF_IN
IN
Input Buffers for memory outputs.
46
FBOUT
OUT
Memory feed back output.
47
GND
PWR
Ground pin.
48
CPUT1_CS
OUT
True clock of differential pair 2.5V push-pull CPU outputs.
49
CPUT0_CS
OUT
True clock of differential pair 2.5V push-pull CPU outputs.
50
VDDCPU2.5
PWR
Power pin for the CPUCLKs. 2.5V
51
VDDCPU3.3
PWR
Power pin for the CPUCLKs. 3.3V
52
CPUCLKC/CPUCLKODC
OUT
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
53
CPUCLKT/CPUCLKODT
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
54
GND
PWR
Ground pin.
55
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
56
Vtt_PWRGD#**/REF1
I/O
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
DESCRIPTION
Mode Pin - Power Management Input Control
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| ICS950908BGLF | 功能描述:IC TIMING CTRL HUB P4 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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| ICS951402 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 processor |
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