參數(shù)資料
型號: ICS951901yFLF-T
英文描述: Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
中文描述: 可編程頻率發(fā)生器
文件頁數(shù): 15/19頁
文件大小: 180K
代理商: ICS951901YFLF-T
15
ICS951901
0670B—07/15/04
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the
ICS94209
. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94209.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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