參數(shù)資料
型號: ICS952004
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85
中文描述: 可編程定時控制中心,為小四至⑩⑩處理器
文件頁數(shù): 18/19頁
文件大?。?/td> 173K
代理商: ICS952004
18
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Integrated
Circuit
Systems, Inc.
ICS952004
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values.
The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
P
O
T
S
_
U
P
C
T
U
P
C
C
U
P
C
1
l
m
r
N
l
m
r
N
0
t
M
*
f
t
o
CPU_ST OP #
CPUT
CPUC
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