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參數(shù)資料
| 型號(hào)： | ICS952601yFLFT |
| 英文描述： | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| 中文描述： | 可編程定時(shí)控制中心⑩處理器的下一代?、?/td> |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 181K |
| 代理商： | ICS952601YFLFT |
3
Integrated
Circuit
Systems, Inc.
ICS952601
0701G—10/13/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for SMBus circuitry, 5V tolerant.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
30
31
32
33
34
SDATA
48MHz_USB
48MHz_DOT
GND
VDD48
I/O
OUT
OUT
PWR
PWR
35
Vtt_PWRGD#
IN
36
VDD
PWR
37
SRCCLKC
OUT
38
SRCCLKT
OUT
39
GND
PWR
40
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
42
VDDCPU
PWR
43
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
45
GND
PWR
46
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic
0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up of
150K nominal
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
48
VDDCPU
PWR
49
PCI_STOP#
IN
50
CPU_STOP#
IN
51
FS_A
IN
52
IREF
OUT
53
54
55
56
GND
GNDA
VDDA
FS_B
PWR
PWR
PWR
IN
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS952601YGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
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| ICS952607 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952607YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
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