- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67708 > ICS952606YFLFT (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | ICS952606YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE, MO-118, SSOP-48 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 162K |
| 代理商： | ICS952606YFLFT |
3
Integrated
Circuit
Systems, Inc.
ICS952606
0717F—06/10/05
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
30
3V66_0
OUT
3.3V 66.66MHz clock output
25
3V66_3/VCH
OUT
3.3V 66.66MHz clock output / 48MHz VCH clock output.
26
3V66_2
OUT
3.3V 66.66MHz clock output
27
VDD3V66
PWR
Power pin for the 3.3V 66MHz clocks.
28
GND
PWR
Ground pin.
29
3V66_1
OUT
3.3V 66.66MHz clock output
30
3V66_0
OUT
3.3V 66.66MHz clock output
31
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
32
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
33
Vtt_Pwrgd#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
34
VDD
PWR
Power supply, nominal 3.3V
35
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
36
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
37
GND
PWR
Ground pin.
38
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
39
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
40
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
41
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
42
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
43
GND
PWR
Ground pin.
44
CPUCLKC_ITP
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
45
CPUCLKT_ITP
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
46
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
47
GND
PWR
Ground pin.
48
VDDA
PWR
3.3V power for the PLL core.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS952607YFLF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS952621YFLF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS952621YGLF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS952623YGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS952624YFLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952607 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952607YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952620CFLF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS952620CFLFT | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS952621 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。