參數(shù)資料
型號(hào)： ICS952607YFLF-T
元件分類： 圓形連接器
英文描述： Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV01; Number of Contacts:6; Connector Shell Size:9; Connecting Termination:Crimp; Circular Shell Style:Straight Receptacle; Body Style:Straight
中文描述： 可編程定時(shí)控制中心，為下一代P4處理器
文件頁(yè)數(shù)： 10/21頁(yè)
文件大小： 214K
代理商： ICS952607YFLF-T
10
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
0734—07/16/04
Table 4: Mode Selection Table
Mode
IIC Control
CPU M/N Overclocking
SRC M/N Overclocking
AGP/PCI M/N Overclocking
Standard Overclock Mode
Byte 5 bit(6:5) = 00
Byte 11 & 12
Byte 11 & 12
Byte 11 & 12
CPU Overclock Mode
Byte 5 bit(6:5) = 01
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Byte 5 & 6 (asynchronous)
Graphic Overclock Mode
Byte 5 bit(6:5) = 10
Byte 11 & 12
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Latch input shoud be set as
FS(4:0) = 10xxx. CPU & SRC
have spread.
CPU/SRC overclock by Byte
11&12 AGP/PCI overclock by
Byte 5&6 asynchronously.
Simple async AGP/PCI
overclocking w/o using M/N
programming.
Spreading
All clocks have spread.
Only CPU clocks have spread.
Remark
All clocks oveclock together by
Byte 11&12 M/N programming.
CPU overclock by Byte 11&12
SRC/AGP/PCI overclock by Byte
5&6 asynchronously.
SRC can be kept at 100 w/o
spread yet AGP/PCI can be
overclocked.
Mode B (B6&B3 bit 7)
AGP/PCI
can be selected to be overclock
from 66/33, 72/36 or 80/40.
Simple async AGP/PCI
overclocking w/o using M/N
programming.
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7
0
0
1
Byte3 Bit7
0
1
0
3V66/PCI Frequency
66.66/33.33
80.00/40.00
72.73/36.36
I
2
C Table: Vendor & Revision ID Register
Control
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASEL0
N PLL2 Div6
N PLL2 Div5
N PLL2 Div4
N PLL2 Div3
N PLL2 Div2
N PLL2 Div1
N PLL2 Div0
3V66/PCI Freq Select
RW
RW
RW
RW
RW
RW
RW
RW
0
X
X
X
X
X
X
X
I
2
C Table: Vendor & Revision ID Register
Control
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
X
X
X
X
0
0
0
1
-
-
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
The decimal representation of N PLL2 Div
(6:0) + 8 is equal to VCO divider value for
PLL2.
0
1
Byte 6
Pin #
Name
-
-
-
-
-
-
PWD
-
-
N Divider
Programming bits for
Async mode 2&3
See Table 4: Async AGP/PCI Freq Table
-
Type
-
-
-
VENDOR ID
PWD
-
-
-
-
REVISION ID
Byte 7
Pin #
Name
0
Type
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