- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362809 > ICS952623YFT Programmable Timing Control Hub for Next Gen P4 processor PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS952623YFT |
| 英文描述： | Programmable Timing Control Hub for Next Gen P4 processor |
| 中文描述： | 可編程定時(shí)控制中心，為下一代P4處理器 |
| 文件頁(yè)數(shù)： | 20/27頁(yè) |
| 文件大?。?/td> | 329K |
| 代理商： | ICS952623YFT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)
20
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
l
n
g
S
#
D
P
n
P
n
P
S
_
U
#
p
o
t
P
C
p
t
o
B
t
S
_
U
P
C
e
T
n
B
w
d
r
w
P
t
e
T
e
a
s
u
p
p
o
p
t
t
S
u
-
n
O
o
N
e
a
s
u
p
p
p
t
o
u
t
O
S
}
U
P
C
1
1
X
X
g
n
n
u
R
g
n
n
u
R
}
U
P
C
1
0
0
X
g
n
n
u
R
6
x
f
@
n
e
v
D
}
U
P
C
1
0
1
X
g
n
n
u
R
e
}
U
P
C
0
X
X
0
2
x
f
@
n
e
v
D
2
x
f
@
n
e
v
D
}
U
P
C
0
X
X
1
e
e
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
l
n
g
S
#
D
P
n
P
n
P
S
_
C
#
p
o
t
P
p
t
B
o
t
S
_
C
P
e
T
n
B
w
d
r
w
P
t
e
T
e
a
t
p
u
p
p
o
t
t
S
-
O
n
o
N
u
e
a
t
u
p
p
t
p
u
o
O
t
S
C
R
S
1
1
X
X
g
n
n
u
R
g
n
n
u
R
C
R
S
1
0
0
X
g
n
n
u
R
6
x
f
@
n
e
v
D
C
R
S
1
0
1
X
g
n
n
u
R
e
C
R
S
0
X
X
0
2
x
f
@
n
e
v
D
2
x
f
@
n
e
v
D
C
R
S
0
X
X
1
e
e
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Differential Clock Tristate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS952623YGT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623 | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YFT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YGT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS95V847 | 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952623YGT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952702 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952702YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952703 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952703BF | 功能描述:IC TIMING CTRL HUB K7 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。