參數(shù)資料
型號： ICS952623YFT
英文描述： Programmable Timing Control Hub for Next Gen P4 processor
中文描述： 可編程定時控制中心，為下一代P4處理器
文件頁數(shù)： 11/27頁
文件大?。?/td> 329K
代理商： ICS952623YFT
11
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
I
2
C Table: Read-Back Register
Byte 0
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
Type
-
-
-
-
0
1
PWD
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
Bit 3
R
X
Bit 2
CPU_STOP#
R
X
Bit 1
FSB
R
X
Bit 0
FSA
R
X
I
2
C Table: Spreading and Device Behavior Control Register
Pin #
Byte 1
Name
Control Function
SRC Free-Running
Control
Output Control
Type
0
1
PWD
Bit 7
SRC/SRC#
RW
FREE-RUN
STOPPABLE
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRC
RW
RW
RW
RW
RW
RW
RW
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
1
1
1
1
1
1
1
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
Output Control
Output Control
Output Enable
I
2
C Table: Output Control Register
Byte 2
Pin #
Name
SRC_PD#
Drive Mode
SRC_Stop#
Drive Mode
CPUT2_PD# Drive
Mode
CPUT1_PD# Drive
Mode
CPUT0_PD# Drive
Mode
CPUT2_Stop Drive
Mode
CPUT1_Stop Drive
Mode
CPUT0_Stop Drive
Mode
Control Function
Type
0
1
PWD
Bit 7
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
RW
Driven
Hi-Z
0
Bit 4
RW
Driven
Hi-Z
0
Bit 3
RW
Driven
Hi-Z
0
Bit 2
RW
Driven
Hi-Z
0
Bit 1
RW
Driven
Hi-Z
0
Bit 0
RW
Driven
Hi-Z
0
RESERVED
RESERVED
0:driven when stopped
1: Tri-stated
0:driven in PD#
1: Tri-stated
-
READBACK
READBACK of CPU(2:0)
Frequency
READBACK
RESERVED
RESERVED
-
-
-
-
-
-
-
37,38
37,38
46,47
43,44
40,41
46,47
43,44
40,41
37,38
37,38
CPU FREE-RUNNING
CONTROL
46,47
43,44
40,41
46,47
43,44
40,41
相關(guān)PDF資料
PDF描述
ICS952623YGT Programmable Timing Control Hub for Next Gen P4 processor
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參數(shù)描述
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