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參數(shù)資料
| 型號(hào)： | ICS95V850AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.240 INCH, LEAD FREE, MO-153, TSSOP-48 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | ICS95V850AGLF |
9
ICS95V850
0458F—08/02/05
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
7) Terminate differential CLK_IN and FB_IN traces after
routing to buffer pads.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R9,R12
120
0603
R9
4.7
0603
U1
ICS95V850
TSSOP48
Recommended Layout for the ICS95V850
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| ICS95V850AGLFT | 功能描述:IC CLK DVR PLL 1:10 48TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類(lèi)型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS95V850AGT | 功能描述:IC CLK DVR PLL 1:10 48TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS95V857 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
| ICS95V857_09 | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
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