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參數(shù)資料
| 型號： | ICS95V857CKLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DVR PLL 1:10 40VFQFN |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | 時鐘緩沖器/驅(qū)動器，零延遲緩沖器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR |
| 輸入： | 時鐘 |
| 輸出： | SSTL-2 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 233MHz |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-VFQFPN（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 95V857CKLF |
3
ICS95V857C
1190A—12/16/05
Pin Descriptions
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This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
The ICS95V857C is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the ICS95V857C clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The
ICS95V857C is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V857C is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS95V857CKLF8 | 功能描述:IC CLK DVR PLL 1:10 40VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS95V857CKLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
| ICS95V857CLLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
| ICS95V860 | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| ICS95V860YHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
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