參數(shù)資料
型號(hào): ICS95V857YG-130LF
元件分類: 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 0.240 INCH, TSSOP-48
文件頁數(shù): 9/13頁
文件大?。?/td> 188K
代理商: ICS95V857YG-130LF
5
ICS95V857 -XXX
Preliminary Product Preview
0674I—03/28/03
Recommended Operating Condition (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD, AVDD
2.3
2.7
V
CLKT, CLKC, FB_INC
VDD/2 - 0.18
V
PD#
-0.3
0.7
V
CLKT, CLKC, FB_INC
VDD/2 + 0.18
V
PD#
1.7
VDD + 0.6
V
DC input signal voltage
(note 2)
-0.3
VDD
V
DC - CLKT, FB_INT
0.36
VDD + 0.6
V
AC - CLKT, FB_INT
0.7
VDD + 0.6
V
Output differential cross-
voltage (note 4)
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
Input differential cross-
voltage (note 4)
VIX
VDD/2 - 0.2
VDD/2 + 0.2
V
High level output
current
IOH
-4.5
mA
Low level output current
IOL
4.5
mA
Input slew rate
SR
14
V/ns
Operating free-air
temperature
TA
085
°C
Differential input signal
voltage (note 3)
VID
Low level input voltage
VIL
High level input voltage
VIH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
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