參數(shù)資料
型號: ICS98UAE877AHLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC CLOCK DRIVER 1.8V LP 52-BGA
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2011
標準包裝: 364
類型: 時鐘緩沖器/驅(qū)動器,零延遲緩沖器,多路復用器
PLL:
主要目的: 存儲器,DDR2
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 410MHz
電源電壓: 1.425 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 52-VFBGA
供應商設備封裝: 52-CABGA(4.5x7.0)
包裝: 托盤
其它名稱: 98UAE877AHLF
ICS98UAE877A
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
8
ICS98UAE877A
7181/3
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V.
Symbol
Parameter1
1
The PLL must be able to handle spread spectrum induced skew.
Conditions
Min.
Max.
Units
freqOP
Max Clock Frequency2
2
Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is
not required to meet the other timing parameters. (Used for low speed system debug.)
1.5V ± 0.075V @ 25
° C95
410
MHz
freqAPP
Application Frequency Range3
3
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
1.5V ± 0.075V @ 25
° C160
410
MHz
dTIN
Input Clock Duty Cycle
40
60
%
TSTAB
CLK Stabilization4
4
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t
), after power-up.
During normal operation, the stabilization time is also the time required for the integrated PLL circuit to ob-
tain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state,
enter the power-down mode and later return to active operation. CLK and CLK may be left floating after
they have been driven low for one complete clock cycle.
9
s
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