參數(shù)資料
型號: ICS9DB106YFLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28
文件頁數(shù): 8/14頁
文件大?。?/td> 189K
代理商: ICS9DB106YFLFT
IDTTM/ICSTM 6 Output PCI Express* Buffer with CLKREQ# Function
ICS9DB106
REV E 08/06/07
ICS9DB106
6 Output PCI Express* Buffer with CLKREQ# Function
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
CLK_INT
IN
"True" reference clock input.
3
CLK_INC
IN
"Complementary" reference clock input.
4
**CLKREQ1#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects
which outputs are controlled.
0 = enabled, 1 = tri-stated
5
PCIEXT0
OUT
True clock of differential PCI_Express pair.
6
PCIEXC0
OUT
Complement clock of differential PCI_Express pair.
7
VDD
PWR
Power supply, nominal 3.3V
8
GND
IN
Ground pin.
9
PCIEXT1
OUT
True clock of differential PCI_Express pair.
10
PCIEXC1
OUT
Complement clock of differential PCI_Express pair.
11
PCIEXT2
OUT
True clock of differential PCI_Express pair.
12
PCIEXC2
OUT
Complement clock of differential PCI_Express pair.
13
VDD
PWR
Power supply, nominal 3.3V
14
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
15
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
16
VDD
PWR
Power supply, nominal 3.3V
17
PCIEXC3
OUT
Complement clock of differential PCI_Express pair.
18
PCIEXT3
OUT
True clock of differential PCI_Express pair.
19
PCIEXC4
OUT
Complement clock of differential PCI_Express pair.
20
PCIEXT4
OUT
True clock of differential PCI_Express pair.
21
GND
PWR
Ground pin.
22
VDD
PWR
Power supply, nominal 3.3V
23
PCIEXC5
OUT
Complement clock of differential PCI_Express pair.
24
PCIEXT5
OUT
True clock of differential PCI_Express pair.
25
**CLKREQ4#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects
which outputs are controlled.
0 = enabled, 1 = tri-stated
26
IREF
OUT
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
相關PDF資料
PDF描述
ICS9DB108YGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
ICS9DB108YFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
ICS9DB108YGT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
ICS9DB108YGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
ICS9DB202CF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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