參數(shù)資料
型號: ICS9DB801C
廠商: Integrated Device Technology, Inc.
英文描述: Eight Output Differential Buffer for PCI Express (50-200MHz)
中文描述: 8個(gè)輸出差分緩沖器的PCI Express(50 - 200MHz的)
文件頁數(shù): 3/19頁
文件大小: 215K
代理商: ICS9DB801C
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C REV C 08/16/07
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
3
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
SRC_DIV#
INPUT
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
2
3
4
5
VDD
GND
SRC_IN
SRC_IN#
POWER
POWER
INPUT
INPUT
6
OE_0
INPUT
7
OE_3
INPUT
8
9
10
11
12
13
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
14
OE_1
INPUT
15
OE_2
INPUT
16
17
18
19
20
21
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
22
BYPASS#/PLL
INPUT
23
24
SCLK
SDATA
INPUT
I/O
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