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參數(shù)資料
| 型號： | ICSLV810FIT |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 0.209 INCH, SSOP-20 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 243K |
| 代理商： | ICSLV810FIT |
Buffer/Clock Driver
MDS LV810 F
6
Revision 101305
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Note1: This parameter is not tested, guaranteed by design.
AC Electrical Characteristics—Bank A
VDDA = 2.5 V, Ambient Temperature -40
° C to +85° C
Input High Current
II
VDDC = max,
VIN = VDD (max)
20
A
Input Capacitance
CIN
VIN = 0V, Note1
5
6.0
pF
Output Capacitance
COUT
VOUT = 0V,
Note 1
5.5
8.0
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Skew: skew between
outputs of same package
tSK(0)
CL = 3 pF,
RL = 500
Figure 3
-200
200
ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P)
CL = 3 pF,
RL = 500
Figure 4
-200
200
ps
Propagation Delay
tpLH / tpHL
CL = 3 pF,
RL = 500
Figure 2
1.5
2.6
3.5
ns
Part to Part Skew
tSK(t)
CL = 3 pF,
RL = 500
Figure 5
-650
650
ps
Output Rise Time
20% to 80%
tr(o)
CL = 3 pF,
RL = 500
0.8
ns
Output Fall Time
80% to 20%
tf(o)
CL = 3 pF,
RL = 500
0.8
ns
Additive Jitter
tJ
All Outputs
50
ps
Duty Cycle
Measured at VDD/2
DC
CL = 3 pF,
RL = 500
45
55
%
Duty Cycle, VDDA=1.8V
DC
40
50
60
%
Output Frequency Range
1
133
MHz
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
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| ICSLV810RILFT | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
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| ICSLV810FIT | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICSLV810SIT | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICSLV810SILF | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
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| ICSLV810RI | 制造商:ICS 制造商全稱:ICS 功能描述:Buffer/Clock Driver |
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