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參數(shù)資料
| 型號(hào)： | ICSLV810RIT |
| 英文描述： | Buffer/Clock Driver |
| 中文描述： | 緩沖器/時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | ICSLV810RIT |
Buffer/Clock Driver
MDS LV810 F
12
Revision 101305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICSLV810
Revision History
Rev.
Originator
Date
Description of Change
A
P.Griffith
03/25/05
New device/datasheet.
B
P.Griffith
05/02/05
Released from Preliminary to final; changed Short Circuit Current parameter in 2.5 V DC
Char table to ±80 mA; changed Short Circuit Current parameter in 1.5 V DC Char table to
±35 mA
C
P.Griffith
05/12/05
Added bullet in “Features” for operating voltage of 2.5 V on Bank A and specified that
operating voltages of 1.5 and 2.5 V are on Banks B and C; changed block diagram input
and pin 1 from IN to CLKIN; removed +1.5 V spec from pin 4 and pin 8 descriptions; added
“VDDA + 1.2 V” to “All Inputs and Outputs” section of Absolute Maximum Ratings; added
min and max values for Banks A, B, and C “Power Supply Voltage” in Recommended
Operating Conditions; expanded DC Electrical Char tables in to include a separate table
for Banks A, B, and C; expanded AC Electrical Char tables in to include a separate table
for Banks A, B, and C;
D
P.Griffith
06/21/05
Added 209 mil 20-pin SSOP package and ordering info.
E
K. Beckmeyer
07/27/05
Specified operating voltage on Bank A from 1.5V to 2.5V; Added figures 4 and 5 on page
10 to explain Pulse Skew and Part-to-Part Skew; Changed Output Frequency Max
Specification to 133MHz in AC Electrical Char tables for Banks A, B, and C; Added Duty
Cycle Spec for VDD = 1.5V in AC Electrical Char tables for Banks A, B, C; Changed CLK
conditions in DC Electrical Char tables on Banks B and C; removed SOIC package.
F
K. Beckmeyer
10/13/05
Added “LF” packaging and ordering info to both “R” and”F” packages.
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