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參數(shù)資料
| 型號： | ICSSSTUA32866BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ICSSSTUA32866BHLFT |
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25
ICSSSTUA32866B
1054A—01/28/05
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (VDD =1.8 V± 0.1V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 28 — Load circuit, error output measurements
—
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
RL = 1K
VDD
LVCMOS
RST#
Input
PLH
t
Output
Waveform 2
CC
V/2
0.15 V
CC
V
0 V
OH
V
0 V
Figure 29
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Timing
Inputs
Output
Waveform 1
PHL
t
ICR
V
CC
V
/2
ICR
V
VI(PP)
CC
V
OL
V
Timing
Inputs
Output
Waveform 2
PHL
t
ICR
V
ICR
V
VI(PP)
OH
V
0
0.15 V
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
Figure 30
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
Figure 31
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