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參數(shù)資料
| 型號(hào)： | ICSSSTUF32866EHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | GREEN, MO-205CC, LFBGA-96 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 310K |
| 代理商： | ICSSSTUF32866EHLFT |
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26
ICSSSTUF32866E
1038B—05/03/05
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (VDD =1.8 V± 0.1V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
VTT = VDD/2
tPLH and tPHL are the same as tPD.
VI(PP) = 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
VTT = VDD/2
tPLH and tPHL are the same as tPD.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
VOH
VOL
OUTPUT
tPLH
002aaa375
VTT
VICR
tPHL
CK
Vi(p-p)
tPHL
002aaa376
LVCMOS RST#
INPUT
OUTPUT
VTT
VDD/2
VIH
VIL
VOH
VOL
DUT
Out
Test Point
RL =
CL = 5 pF
(see Note A)
1 k
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