- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360789 > ICSSSTV16859CG-T DDR 13-Bit to 26-Bit Registered Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | ICSSSTV16859CG-T |
| 英文描述： | DDR 13-Bit to 26-Bit Registered Buffer |
| 中文描述： | 復(fù)員13位至26位注冊(cè)緩沖區(qū) |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 98K |
| 代理商： | ICSSSTV16859CG-T |
2
ICSSSTV16859C
0703A—10/15/02
General Description
The 13-bit-to-26-bit ICSSSTV16859C is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Pin Configuration (64-Pin TSSOP)
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16859C supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
R
E
2
1
,
4
,
3
3
6
,
5
,
3
,
3
,
4
,
4
4
,
6
,
5
8
4
9
4
,
4
,
3
5
5
4
B
M
,
1
U
N
N
1
I
P
E
M
A
)
1
N
N
Q
I
P
E
U
P
P
Y
T
T
U
N
O
I
P
I
R
C
S
E
D
2
3
2
5
,
5
,
,
,
3
,
,
2
1
,
1
,
,
T
O
t
p
o
a
D
,
D
N
G
R
W
P
d
n
u
o
G
4
-
5
6
,
5
,
5
,
4
,
5
2
6
,
2
,
1
,
3
,
,
3
Q
D
D
V
R
W
P
l
n
m
o
n
V
5
,
g
a
v
y
p
u
s
t
p
O
)
1
D
T
U
P
N
I
t
p
n
a
D
K
K
D
D
E
S
E
R
L
L
C
C
V
E
V
T
T
U
U
R
U
U
P
P
W
P
P
N
N
P
N
N
I
I
t
p
p
n
V
5
n
k
c
,
g
)
a
v
k
c
o
o
a
v
w
o
e
v
a
c
n
e
r
a
r
a
m
y
p
m
e
u
e
v
o
P
g
e
N
e
C
s
e
R
t
p
n
#
t
v
s
t
0
6
l
n
m
o
n
1
#
T
F
R
T
T
I
I
l
n
m
o
n
V
5
,
g
e
R
5
5
E
B
M
U
2
1
,
3
,
2
,
3
2
N
N
,
I
P
E
M
A
)
1
D
N
G
D
D
V
)
1
D
L
C
K
L
C
D
V
S
E
R
R
V
r
e
C
N
N
Q
I
P
E
U
R
R
T
U
U
U
R
W
U
P
U
P
W
P
P
Y
T
W
P
W
P
P
N
P
N
P
N
P
N
N
P
T
U
N
O
I
P
I
R
C
S
E
D
6
5
,
,
8
4
,
3
4
3
5
6
4
,
3
8
3
2
3
-
1
1
,
T
O
t
p
o
d
n
t
n
e
v
o
P
v
g
e
N
e
C
t
s
e
R
t
p
n
u
o
G
a
D
o
G
p
O
a
D
u
5
7
5
4
,
4
,
4
,
4
,
,
2
,
1
2
,
,
2
Q
l
n
m
o
n
V
5
,
g
a
v
y
p
t
p
a
m
m
e
y
p
u
v
a
e
M
(
d
n
u
s
,
I
I
I
3
3
K
T
T
t
p
p
n
V
5
n
k
c
,
g
)
a
v
k
c
a
p
k
c
o
o
a
v
w
o
e
e
c
n
2
F
L
r
r
a
#
t
5
,
2
D
E
E
l
n
m
o
n
s
#
T
F
P
T
T
I
I
l
n
m
o
n
V
5
)
o
e
,
g
g
a
D
A
R
Pin Configuration (56-Pin MLF2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICSSSTV16859yG-T | DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV32852 | DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTV32852yHT | DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTVA16857YGLF-T | DDR 14-Bit Registered Buffer |
| ICSSSTVA16857 | DDR 14-Bit Registered Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTV16859YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YK | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV32852 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTV32852YHT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTVA16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。