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參數(shù)資料
| 型號： | ICSSSTV32852yHT |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | 復(fù)員24位到48位注冊緩沖區(qū) |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 129K |
| 代理商： | ICSSSTV32852YHT |
2
ICSSSTV32852
0513F—05/13/03
General Description
The 24-bit-to-48-bit
ICSSSTV32852
is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2 I/
O levels, except for the LVCMOS RESET# input.
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Pin Configuration
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only.
ICSSSTV32852
supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the
logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET#
must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-
up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
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PDF描述 |
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| ICSSSTVA16857YGLF-T | DDR 14-Bit Registered Buffer |
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| ICSSSTVA16859B | DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTVA16859BGLF-T | DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTVA16859BG-T | DDR 13-Bit to 26-Bit Registered Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICSSSTVA16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTVA16857YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTVA16859B | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTVA16859BGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTVA16859BG-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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