參數(shù)資料
型號: ICX424AQ
廠商: Sony Corporation
英文描述: Diagonal 6mm Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
中文描述: 對角線毫米漸進式掃描CCD與廣場像素圖像傳感器的彩色攝像機
文件頁數(shù): 4/27頁
文件大?。?/td> 255K
代理商: ICX424AQ
4
ICX424AQ
Clock Voltage Conditions
Bias Conditions
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same voltage as the V
L
power
supply for the V driver should be used.
2
Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.
3
Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics
Supply current
Item
I
DD
Symbol
7
Min.
Unit
mA
Remarks
Typ.
Max.
9
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Item
V
VT
V
VH02
V
VH1
, V
VH2
, V
VH3
V
VL1
, V
VL2
, V
VL3
V
VL1
, V
VL2
, V
VL3
V
φ
1
, V
φ
2
, V
φ
3
| V
VL1
V
VL3
|
V
VHH
V
VHL
V
VLH
V
VLL
V
φ
H
V
HL
V
CR
V
φ
RG
V
RGLH
V
RGLL
V
RGL
V
RGLm
V
φ
SUB
Symbol
14.55
0.05
0.2
7.8
8.0
6.8
4.75
0.05
0.8
4.5
21.5
Min.
15.0
0
0
7.5
7.5
7.5
5.0
0
2.5
5.0
22.5
Typ.
15.45
0.05
0.05
7.2
7.0
8.05
0.1
1.0
2.3
1.0
1.0
5.25
0.05
5.5
0.8
0.5
23.5
Max.
Unit
1
2
2
2
2
2
2
2
2
2
2
3
3
3
4
4
4
5
Waveform
Diagram
V
VH
= V
VH02
V
VL
= V
VL1
(V
VL3
)/2
(During 24.54MHz)
V
VL
= V
VL1
(V
VL3
)/2
(During 12.27MHz)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Cross-point voltage
Low-level coupling
Low-level coupling
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Item
V
DD
V
L
φ
SUB
φ
RG
Symbol
15.0
1
2
3
Min.
14.55
V
Unit
Remarks
Typ.
Max.
15.45
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