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參數(shù)資料
| 型號： | ID82C50A |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Asynchronous Communications Element |
| 中文描述： | 1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 101K |
| 代理商： | ID82C50A |
12
Modem Status Registers. The contents of the Interrupt
Enable Register are indicated in Table 3 and are described
below.
IER(0):
When programmed high (IER(0) = Logic 1), IER(0)
enables Received Data Available interrupt.
IER(1):
When programmed high (IER(1) = Logic 1), IER(1)
enables the Transmitter Holding Register Empty interrupt.
IER(2):
When Programmed high (IER(2) = Logic 1), IER(2)
enables the Receiver Line Status interrupt.
IER(3):
When programmed high (IER(3) = Logic 1), IER(3)
enables the Modem Status interrupt.
IER(4) - IER(7):
These four bits of the IER are logic 0.
FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE
INTRPT
PIN 30
DR (LSR BIT 0)
ERBFI (IER BIT 0)
OE (LSR BIT 1)
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 2)
DCTS (MSR BIT 0)
DDSR (MSR BIT 1)
TERI (MSR BIT 2)
DDCD (MSR BIT 3)
EDSSI (IER BIT 3)
THRE (LSR BIT 5)
ETBEI (IER BIT 1)
TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY
(NOTE: See Table 1 for how to access these registers.)
REGISTER
MNEMONIC
REGISTER BIT NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RBR
(Read Only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
THR
(Write Only)
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
IER
0
0
0
0
(EDSSI)
Enable
Modem
Status
Interrupt
(ELSI)
Enable
Receiver
Line
Status
Interrupt
(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ERBFI)
Enable
Received
Data
Available
Interrupt
IIR
(Read Only)
0
0
0
0
0
Interrupt ID
Bit (1)
Interrupt ID
Bit (0)
“0” 1F
Interrupt
Pending
LCR
(DLAB)
Divisor
Latch
Access
Bit
Set Break
Stick Parity
(EPS)
Even Parity
Select
(PEN)
Parity
Enable
(STB)
Number
of Stop
Bits
(WLSB1)
Word
Length
Select
Bit 1
(WLSB0)
Word
Length
Select
Bit 0
MCR
0
0
0
Loop
Out 2
Out 1
(RTS)
Request
to Send
(DTR)
Data
Terminal
Ready
LSR
0
(TEMT)
Transmitter
Empty
(THRE)
Transmitter
Holding
Register
Empty
(BI)
Break
Interrupt
(FE)
Framing
Error
(PE)
Parity
Error
(OE)
Overrun
Error
(DR)
Data
Ready
MSR
(DCD)
Data
Carrier
Detect
(RI)
Ring
Indicator
(DSR)
Data
Set
Ready
(CTS)
Clear
to
Send
(DDCD)
Delta
Data
Carrier
Detect
(TERI)
Trailing
Edge
Ring
Indicator
(DDSR)
Delta
Data
Set
Ready
(DCTS)
Delta
Clear
to
Send
SCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB, Data Bit 0 is the first bit transmitted or received.
82C50A
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