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參數(shù)資料
| 型號(hào)： | ID82C82 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER BUS OCT LATCHING 20DIP |
| 標(biāo)準(zhǔn)包裝： | 190 |
| 類(lèi)型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 20-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-CDIP |
| 包裝： | 管件 |
278
Timing Waveforms
AC Electrical Specifications VCC = 5.0V ±10%;
TA = 0
oC to +70oC (C82C82);
CL = 300pF (Note 1), Freq = 1MHz TA = -40
oC to +85oC (I82C82);
TA = -55
oC to +125oC (M82C82)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(1)
TIVOV
Propagation Delay Input to Output
-
35
ns
Notes 2, 3
(2)
TSHOV
Propagation Delay STB to Output
-
55
ns
Notes 2, 3
(3)
TEHOZ
Output Disable Time
-
35
ns
Notes 2, 3
(4)
TELOV
Output Enable Time
-
50
ns
Notes 2, 3
(5)
TIVSL
Input to STB Setup Time
0
-
ns
Notes 2, 3
(6)
TSLIX
Input to STB Hold Time
25
-
ns
Notes 2, 3
(7)
TSHSL
STB High Time
25
-
ns
Notes 2, 3
(8)
TR, TF
Input Rise/Fall Times
-
20
ns
Notes 2, 3
NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between VIL - 0.4V and VIH +0.4V.
TR, TF (8)
TIVSL (5)
TSLIX
(6)
2.0V
0.8V
VOH -0.1V
TELOV (4)
VOL +0.1V
2.4V
0.8V
TEHOZ (3)
TSHSL (7)
(1)
TIVOV
TSHOV (2)
INPUTS
STB
OUTPUTS
OE
Test Load Circuits
NOTE: Includes stray and jig capacitance.
OUTPUT
TEST
300pF
150
1.7V
POINT
(NOTE)
TIVOV, TSHOV, TELOV
OUTPUT
TEST
50pF
300
0.6V
POINT
(NOTE)
TEHOZ OUTPUT HIGH DISABLE
OUTPUT
TEST
50pF
300
3.3V
POINT
(NOTE)
TEHOZ OUTPUT LOW DISABLE
82C82
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