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參數(shù)資料
| 型號： | ID83C154T-L16 |
| 英文描述： | CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| 中文描述： | 的CMOS 0至36 MHz的單芯片8位微控制器 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 354K |
| 代理商： | ID83C154T-L16 |
Rev.F (14 Jan. 97)
12
MATRA MHS
If C/T
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
Table 3. Content of the SFRS after a reset triggered
by the watchdog.
REGISTER
CONTENT
PC
ACC
B
PSW
SP
DPTR
P0-P3
IP
IE
TMOD
TCON
T2CON
TH0
TL0
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
IOCON
PCON
000H
00H
00H
00H
07H
0000H
0FFH
0X000000B
0X000000B
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Indeterminate
00H
000X0000B
As there are no precautions for protecting bit WDT
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions :
–
SETB and CLR x
in preference to the byte handling instructions :
–
MOV IOCON, # XXH, ORL IOCON, #XXH,
–
ANL IOCON, #XXH
External Counting in Power-down Mode
(PD = PCON.1 = 1)
In the power-down mode, the oscillator is turned off
and the 83C154’s activity is frozen. However, if an
external clock is connected to one of the two inputs,
T1/T0, TIMER/COUNTERS 0 and 1 can continue to
operate.
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC : 24.
The overflow of either counter TF0 or TF1 causes an
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = 1).
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