參數(shù)資料
型號: IDT2308A-4DCI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC CLOCK MULT ZD STD DRV 16-SOIC
產(chǎn)品變化通告: Product Discontinuation 13/May/2009
標(biāo)準(zhǔn)包裝: 48
類型: 倍增器,零延遲緩沖器
PLL: 帶旁路
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133.3MHz
除法器/乘法器: 無/是
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
其它名稱: 2308A-4DCI
2
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
PINCONFIGURATION
SOIC/ TSSOP
TOP VIEW
REF
CLKA1
S2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLKA2
GND
CLKB1
FBK
CLKA4
GND
S1
VDD
CLKB2
CLKB3
CLKB4
CLKA3
Symbol
Rating
Max.
Unit
VDD
SupplyVoltageRange
–0.5 to +4.6
V
VI(2)
InputVoltageRange(REF)
–0.5 to +5.5
V
VI
InputVoltageRange
–0.5to
V
(except REF)
VDD+0.5
IIK (VI < 0)
InputClampCurrent
–50
mA
IO
ContinuousOutputCurrent
±50
mA
(VO = 0 to VDD)
VDD or GND
ContinuousCurrent
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(instillair)(3)
TSTG
StorageTemperatureRange
–65to+150
°C
Operating
CommercialTemperature
0 to +70
°C
Temperature
Range
Operating
IndustrialTemperature
-40 to +85
°C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°C and a board trace length of 750 mils.
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Pin Number
FunctionalDescription
REF
1
InputReferenceClock,5VoltTolerantInput
CLKA1(1)
2
Clock Output for Bank A
CLKA2(1)
3
Clock Output for Bank A
VDD
4
3.3V Supply
GND
5
Ground
CLKB1(1)
6
Clock Output for Bank B
CLKB2(1)
7
Clock Output for Bank B
S2(2)
8
Select Input, Bit 2
S1(2)
9
Select Input, Bit 1
CLKB3(1)
10
Clock Output for Bank B
CLKB4(1)
11
Clock Output for Bank B
GND
12
Ground
VDD
13
3.3V Supply
CLKA3(1)
14
Clock Output for Bank A
CLKA4(1)
15
Clock Output for Bank A
FBK
16
PLLFeedbackInput
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
PINDESCRIPTION
ABSOLUTEMAXIMUMRATINGS(1)
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