參數(shù)資料
型號: IDT2309B-1HPGGI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/10頁
文件大?。?/td> 0K
描述: IC CLK BUFFER ZD HI DRV 16-TSSOP
標準包裝: 4,000
類型: 零延遲緩沖器
PLL: 帶旁路
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:9
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133MHz
除法器/乘法器: 無/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 2309B-1HPGGI8
5
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2309B
3.3VZERODELAYCLOCKBUFFER
SWITCHING CHARACTERISTICS (2309B-1H) - INDUSTRIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t1
OutputFrequency
10pFLoad
10
133
MHz
30pFLoad
10
100
Duty Cycle = t2
÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
Duty Cycle = t2
÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55
%
t3
Rise Time
Measured between 0.8V and 2V
1.5
ns
t4
Fall Time
Measured between 0.8V and 2V
1.5
ns
t5
Output to Output Skew
Alloutputsequallyloaded
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode (IDT2309B only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
V/ns
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
175
ps
tLOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2309B-1) - INDUSTRIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t1
OutputFrequency
10pFLoad
10
133
MHz
30pFLoad
10
100
Duty Cycle = t2
÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.8V and 2V
2.5
ns
t4
Fall Time
Measured between 0.8V and 2V
2.5
ns
t5
Output to Output Skew
Alloutputsequallyloaded
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode (IDT2309B only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
0
700
ps
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
50
175
ps
tLOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
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