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參數(shù)資料
| 型號： | IDT23S09T-1DCG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER ZD 2.5V 16-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 23S09T-1DCG8 |
2
COMMERCIALTEMPERATURERANGE
IDT23S09T
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE
PIN CONFIGURATION
SOIC
TOP VIEW
Symbol
Rating
Max.
Unit
VDD
SupplyVoltageRange
–0.5 to +4.6
V
VI(2)
InputVoltageRange(REF)
–0.5 to +5.5
V
VI
InputVoltageRange
–0.5to
V
(except REF)
VDD+0.5
IIK (VI < 0)
InputClampCurrent
–50
mA
IO (VO = 0 to VDD)
ContinuousOutputCurrent
±50
mA
VDD or GND
ContinuousCurrent
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(instillair)(3)
TSTG
StorageTemperatureRange
–65to+150
°C
Operating
CommercialTemperature
0 to +70
°C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
Pin Name
Pin Number
Type
Functional Description
REF(1)
1
IN
Input reference clock, 3.3V tolerant input
CLKA1(2)
2
Out
Output clock for bank A
CLKA2(2)
3
Out
Output clock for bank A
VDD
4, 13
PWR
2.5V Supply
GND
5, 12
GND
Ground
CLKB1(2)
6
Out
Output clock for bank B
CLKB2(2)
7
Out
Output clock for bank B
S2(3)
8
IN
Select input Bit 2
S1(3)
9
IN
Select input Bit 1
CLKB3(2)
10
Out
Output clock for bank B
CLKB4(2)
11
Out
Output clock for bank B
CLKA3(2)
14
Out
Output clock for bank A
CLKA4(2)
15
Out
Output clock for bank A
CLKOUT(2)
16
Out
Output clock, internal feedback on this pin
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
REF
CLKA1
S2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLKA2
GND
CLKB1
CLKOUT
CLKA4
GND
S1
VDD
CLKB2
CLKB3
CLKB4
CLKA3
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