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參數(shù)資料
| 型號(hào)： | IDT29FCT2052AT |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| 中文描述： | 快速CMOS八進(jìn)制注冊(cè)收發(fā)器 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | IDT29FCT2052AT |
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.1
2
PIN CONFIGURATIONS
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A
7
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
E24-1
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CEB
CEA
CPB
CPA
OEA
B
6
B
5
B
4
B
3
B
2
B
1
B
B
7
0
OEB
2629 drw 02
5
6
7
8
9
10
11
L28-1
25
24
23
22
21
20
19
12 13 14 15 16 17 18
4
3
2
1
28 27 26
INDEX
2629 drw 03
B
3
B
2
NC
B
1
B
0
A
5
A
4
A
3
NC
A
2
A
1
A
0
OEB
G
C
C
C
C
O
N
B
4
B
V
A
A
B
6
N
B
7
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
LCC
TOP VIEW
PIN DESCRIPTION
Name
I/O
A
0-7
I/O
B
0-7
I/O
CPA
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs are in the high-impedance state.
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines. When
OEA
is HIGH, the A
0-7
outputs are in the high-impedance state.
I
CEA
I
OEB
I
CPB
I
CEB
I
OEA
I
2629 tbl 01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT29FCT2052BT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT52DT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT2052CT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT52AT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT52BT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT29FCT2052ATDB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT2052ATEB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT2052ATLB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT2052ATP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT2052ATPY | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single 8-bit Bus Transceiver |
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