- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377132 > IDT49ALVCH16823PA (Integrated Device Technology, Inc.) 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD PDF資料下載
參數(shù)資料
| 型號： | IDT49ALVCH16823PA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| 中文描述： | 3.3V的CMOS 18位總線接口觸發(fā)器具有三態(tài)輸出和總線狀態(tài)保持 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 79K |
| 代理商： | IDT49ALVCH16823PA |
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
5
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Min.
150
1
V
CC
= 2.7V
Min.
150
—
V
CC
= 3.3V ± 0.3V
Min.
150
1
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
SU
t
H
t
H
t
H
t
SK(O)
Parameter
Max.
—
5.8
Max.
—
5.2
Max.
—
4.5
Unit
MHz
ns
Propagation Delay
xCLK to xQx
Propagation Delay
xCLR
to xQx
Output Enable Time
xOE
to xQx
Output Disable Time
xOE
to xQx
Pulse Duration,
xCLR
LOW
Pulse Duration, xCLK HIGH or LOW
Set-up Time,
xCLR
inactive
Set-up Time, data LOW before xCLK
↑
Set-up Time, data HIGH before xCLK
↑
Set-up Time,
xCLKEN
LOW before xCLK
↑
Hold Time, data LOW after xCLK
↑
Hold Time, data HIGH after xCLK
↑
Hold Time,
xCLKEN
LOW after CLK
↑
Output Skew
(2)
1
5.4
—
5.2
1.2
4.6
ns
1
6
—
5.7
1
4.8
ns
1.1
5.4
—
4.7
1.3
4.5
ns
3.3
3.3
0.7
1.4
1.1
1.8
0.4
0.7
0.2
—
—
—
—
—
—
—
—
—
—
—
3.3
3.3
0.7
1.6
1.1
1.9
0.5
0.1
0.3
—
—
—
—
—
—
—
—
—
—
—
3.3
3.3
0.8
1.3
1
1.5
0.5
0.8
0.4
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT61ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT62ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT63ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT64ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT65ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT49C25AD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
| IDT49C25ADB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
| IDT49C25AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
| IDT49C25AEB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
| IDT49C25AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。