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參數(shù)資料
| 型號： | IDT54FCT162H272ETPFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER |
| 中文描述： | 快速CMOS 12位同步總線交換 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 138K |
| 代理商： | IDT54FCT162H272ETPFB |
5.5
3
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS
(1)
FUNCTION TABLES
(2)
3071 tbl 04
3071 tbl 05
NOTES:
1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
PIN DESCRIPTION
Signal
A
(1:12)
1B
(1:12)
2B
(1:12
)
CLK
CEA1B
I/O
I/O
I/O
I/O
I
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
(1)
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
(1)
Clock Input.
Clock Enable Input for the A-1B Register. If
CEA1B
is LOW during the rising edge of CLK, data will be clocked
into register A-1B (Active LOW).
Clock Enable Input for the A-2B Register. If
CEA2B
is LOW during the rising edge of CLK, data will be clocked
into register A-2B (Active LOW).
Clock Enable Input for the 1B-A Register. If
CE1B
is LOW during the rising edge of CLK, data will be clocked into
register 1B-A (Active LOW).
Clock Enable Input for the 2B-A Register. If
CE2B
is LOW during the rising edge of CLK, data will be clocked into
register 2B-A (Active LOW).
1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to
A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.
Synchronous Output Enable for A Port (Active LOW).
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
CEA2B
I
CE1B
I
CE2B
I
SEL
I
OEA
I
I
OEB
3071 tbl 01
Inputs
SEL
H
H
Output
A
H
L
A
(1)
H
L
A
(1)
Z
1B
H
L
2B
X
X
CE1B
CE2B
OEA
CLK
↑
↑
↑
↑
↑
↑
↑
L
L
X
X
L
L
X
X
X
X
H
L
H
L
L
H
X
X
X
L
L
L
L
L
X
X
X
X
L
X
X
X
H
X
L
H
Inputs
Outputs
A
H
L
CEA1B CEA2B
OEB
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
1B
H
L
2B
H
L
B
(1)
B
(1)
H
L
B
(1)
Z
Active
L
L
L
L
L
L
H
L
H
L
L
L
H
H
H
H
L
L
L
L
L
L
H
L
B
(1)
B
(1)
B
(1)
Z
Active
X
X
X
H
X
X
H
X
X
L
H
L
Symbol
V
TERM(2)
Terminal Voltage with Respect to
GND
V
TERM(3)
Terminal Voltage with Respect to
GND
Description
Max.
Unit
V
–0.5 to +7.0
–0.5 to
V
CC
+0.5
–65 to +150
–60 to +120 mA
V
T
STG
I
OUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
Storage Temperature
DC Output Current
°
C
3071 tbl 02
NOTE:
1. This parameter is measured at characterization but not tested.
CAPACITANCE
(T
A
= +25
°
C, F = 1.0MH
Z
)
3071 tbl 03
Symbol
C
IN
Parameter
(1)
Input
Capacitance
I/O
Capacitance
Conditions
V
IN
= 0V
Typ.
3.5
Max.
6.0
Unit
pF
C
I/O
V
OUT
= 0V
3.5
8.0
pF
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT54FCT162H272ETPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER |
| IDT54FCT162H272ETPVB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER |
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| IDT54FCT162H501ATE | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS 18-BIT REGISTERED TRANSCEIVER |
| IDT54FCT162H501ATEB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS 18-BIT REGISTERED TRANSCEIVER |
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