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參數(shù)資料
| 型號(hào)： | IDT54FCT16823ETPVB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS 18-BIT REGISTER |
| 中文描述： | 快速CMOS 18位的寄存器 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | IDT54FCT16823ETPVB |
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.16
6
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
2772 tbl 09
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
FCT16823AT/162823AT
FCT16823BT/162823BT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(5)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(5)
R
L
= 500
C
L
= 5pF
(5)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 50pF
R
L
= 500
Min.
(2)
1.5
Max.
10.0
Min.
(2)
1.5
Max.
11.5
Min.
(2)
1.5
Max.
7.5
Min.
(2)
1.5
Max.
8.5
Unit
ns
Propagation Delay
xCLK to xQx
1.5
20.0
1.5
20.0
1.5
15.0
1.5
16.0
t
PHL
Propagation Delay
x
CLR
to xQx
Output Enable Time
x
OE
to xQx
1.5
14.0
1.5
15.0
1.5
9.0
1.5
9.5
ns
t
PZH
t
PZL
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
ns
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
t
PHZ
t
PLZ
Output Disable Time
x
OE
to xQx
1.5
7.0
1.5
8.0
1.5
6.5
1.5
7.0
ns
1.5
8.0
1.5
9.0
1.5
7.5
1.5
8.0
t
SU
Set-up Time HIGH or LOW
xDx to xCLK
Hold Time HIGH or LOW
xDx to xCLK
Set-up Time HIGH or LOW
x
CLKEN
to xCLK
Hold Time HIGH or LOW
x
CLKEN
to xCLK
xCLK Pulse Width
HIGH or LOW
x
CLR
Pulse Width LOW
4.0
—
4.0
—
3.0
—
3.0
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
ns
t
SU
4.0
—
4.0
—
3.0
—
3.0
—
ns
t
H
2.0
—
2.0
—
0
—
0
—
ns
t
W
7.0
—
7.0
—
6.0
—
6.0
—
ns
t
W
6.0
—
7.0
—
6.0
—
6.0
—
ns
t
REM
t
SK
(o) Output Skew
(3)
Recovery Time x
CLR
to xCLK
6.0
—
—
0.5
7.0
—
—
0.5
6.0
—
—
0.5
6.0
—
—
0.5
ns
ns
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