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參數(shù)資料
| 型號： | IDT54FCT388915T100L |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| 封裝： | LCC-28 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T100L |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
4
POWER SUPPLY CHARACTERISTICS
OUTPUT FREQUENCY SPECIFICATIONS
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
T
RISE/FALL
Rise/Fall Times,
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
Duty Cycle Input Duty Cycle,
SYNC Inputs
3052 tbl 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25
°
C ambient.
3. Per TTL driven input. All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f =2Q Frequency
I
LOAD
= Dynamic Current due to load.
3052 tbl 05
Min.
—
Max.
3.0
Unit
ns
10.0
(1)
2Q fmax
MHz
25%
75%
—
Symbol
I
CC
Parameter
Test Conditions
(1)
Min.
—
Typ.
(2)
2.0
Max.
30
Unit
μ
A
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
All Outputs Open
V
IN
= V
CC
–0.6V
(3)
I
CCD
V
IN
= V
CC
V
IN
= GND
—
0.2
0.3
mA/
MHz
C
PD
I
C
Power Dissipation Capacitance
Total Power Supply Current
(6)
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
15pF
—
—
15
30
25
60
pF
mA
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
50
Thevenin termination and 20pF
—
90
120
mA
3052 tbl 07
Max.
(2)
100
100
Symbol
f2Q
Parameter
Min.
40
70
70
133
133
150
150
Unit
MHz
Operating frequency 2Q Output
fQ
fQ/2
Operating frequency Q0-Q4,
Q
5 Outputs
Operating frequency Q/2 Output
20
10
35
17.5
50
25
66.7
33.3
75
37.5
MHz
MHz
相關PDF資料 |
PDF描述 |
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| IDT54FCT388915T100LB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100LB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
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