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參數(shù)資料
| 型號(hào)： | IDT54FCT388915T70JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | 0.050 INCH PITCH, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T70JB |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
5
Symbol
Parameter
Condition
(1)
Load = 50
to
V
CC
/2, C
L
= 20pF
Load = 50
to
V
CC
/2, C
L
= 20pF
Min
.*
0.2
(2)
Max.*
1.5
Unit
ns
t
RISE/FALL
All Outputs
t
PULSE WIDTH (3)
Q,
Q
, Q/2 outputs
(3)
t
PULSE WIDTH
2Q Output
(3)
t
PD
SYNC-FEEDBACK
(3)
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4,
Q
5, Q/2, @ 1.5V
Output Pulse Width
2Q @ 1.5V
SYNC input to FEEDBACK delay
(measured at SYNC0 or 1 and FEEDBACK
input pins)
0.5t
CYCLE
– 0.5
(5)
0.5t
CYCLE
+ 0.5
(5)
ns
0.5t
CYCLE
– 0.7
(5)
0.5t
CYCLE
+ 0.7
(5)
ns
Load = 50
to
V
CC
/2, C
L
= 20pF
0.1
μ
F from LF to
Analog GND
(5)
Load = 50
to
V
CC
/2, C
L
= 20pF
–0.5
+0.5
ns
t
SKEW
r
(rising)
(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising,
Q
5 falling
Time required to acquire
Phase-Lock from time
SYNC input signal is received
Output Enable Time
OE/
RST
(LOW-to-HIGH) to Q, 2Q, Q/2,
Q
Output Disable Time
OE/
RST
(HIGH-to-LOW) to Q, 2Q, Q/2,
Q
—
250
ps
t
SKEW
f
(falling)
(3,4)
t
SKEW
all
(3,4)
—
250
ps
—
350
ps
t
LOCK(6)
1
(2)
10
ms
t
PZH
t
PZL
t
PHZ
t
PLZ
3
(2)
14
ns
3
(2)
14
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
GENERAL AC SPECIFICATION NOTES:
*
PRELIMINARY.
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q,
Q
, Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin. t
LOCK
Max. is with C1 = 0.1
μ
F, t
LOCK
Min. is with C1 = 0.01
μ
F. (Where
C1 is loop filter capacitor shown in Figure 2).
3052 tbl 08
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T70JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70LB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70LB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
| IDT54FCT573ADB | 制造商:Integrated Device Technology Inc 功能描述: |
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