- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377480 > IDT54FCT388915T (Integrated Device Technology, Inc.) 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) PDF資料下載
參數(shù)資料
| 型號： | IDT54FCT388915T |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | 3.3V的低歪曲基于PLL的CMOS時(shí)鐘驅(qū)動(dòng)器，（3態(tài)） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
8
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4,
Q5
) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
25 MHz
input
50 MHz signal
25 MHz feedback signal
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
signal
OE/RST
3052 drw 10
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
50 MHz feedback signal
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
50 MHz
input
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
input
OE/RST
3052 drw 11
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Output Feedback
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
50 MHz signal
12.5 MHz feedback signal
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
input
OE/RST
3052 drw 09
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T150JB | CAP 1.8UF 250/275VAC ECQ-UL |
| IDT54FCT388915T150JB | CAPACITOR .18UF UV BOX TYPE |
| IDT54FCT388915T100J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T100JB | CAP 6.8UF 6V 10% TANT SOLID A-CASE HERMETIC T&R M-MIL-PRF-39003/01 |
| IDT54FCT388915T100L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
| IDT54FCT573ADB | 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。