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參數(shù)資料
| 型號： | IDT54FCT646SOB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS OCTAL TRANSCEIVER/REGISTER |
| 中文描述： | 快速CMOS八端口收發(fā)器/注冊 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 91K |
| 代理商： | IDT54FCT646SOB |
7.18
6
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT646
Com’l.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
54/74FCT646A
Com’l.
Max. Min.
(2)
Max.
54/74FCT646C
Com’l.
Min.
(2)
Mil.
Mil.
Mil.
Symbol
Parameter
Condition
(1)
Max. Min
.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation
Delay
Bus to Bus
C
L
= 50 pF
R
L
= 500
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
5.4
1.5
6.0
ns
t
PZH
t
PZL
Output Enable
Time
G
, DIR to
Bus
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
1.5
7.8
1.5
8.9
ns
t
PHZ
t
PLZ
Output Disable
Time
G
, DIR to
Bus
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
6.3
1.5
7.7
ns
t
PLH
t
PHL
Propagation
Delay Clock
to Bus
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
1.5
5.7
1.5
6.3
ns
t
PLH
t
PHL
Propagation
Delay SBA or
SAB to Bus
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
1.5
6.2
1.5
7.0
ns
t
SU
Set-up Time
HIGH or LOW
Bus to Clock
4.0
—
4.5
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
t
H
Hold Time
HIGH or LOW
Bus to Clock
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
W
Clock Pulse
Width HIGH or
LOW
6.0
—
6.0
—
5.0
—
5.0
—
5.0
—
5.0
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2536 tbl 07
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PDF描述 |
|---|---|
| IDT74FCT646SOB | FAST CMOS OCTAL TRANSCEIVER/REGISTER |
| IDT54FCT646TDB | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT74FCT646TDB | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT54FCT646TSO | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT74FCT646TSO | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
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|---|---|
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