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參數(shù)資料
| 型號： | IDT54FCT810CTDB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FAST CMOS BUFFER/CLOCK DRIVER |
| 中文描述： | FCT SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 107K |
| 代理商： | IDT54FCT810CTDB |
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
4
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay
limits do not imply skew.
3103 tbl 06
IDT54/74FCT810BT
Com'l.
IDT54/74FCT810CT
Com'l.
Mil.
Mil.
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK1
(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min.
(2)
1.5
Max. Min.
(2)
4.5
Max. Min.
(2)
4.9
Max.
4.3
Min
.(2)
1.5
Max.
4.6
Unit
ns
Propagation Delay
IN
A
to OA
n
, IN
B
to
OB
n
Output Rise Time
Output Fall Time
1.5
1.5
—
—
—
1.5
1.5
0.5
—
—
—
2.0
1.5
0.9
—
—
—
1.5
1.5
0.3
—
—
—
2.0
1.5
0.7
ns
ns
ns
t
SK2
(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
t
SK
(p)
Pulse skew: skew between opposite
transitions of same output |(t
PHL
-t
PLH
)|
—
0.7
—
1.1
—
0.6
—
1.0
ns
—
0.7
—
1.2
—
0.7
—
1.1
ns
t
SK
(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Output Enable Time
OE
A
to OA
n
,
OE
B
to
OB
n
Output Disable Time
OE
A
to OA
n
,
OE
B
to
OB
n
—
1.2
—
1.5
—
1.0
—
1.2
ns
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
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