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參數(shù)資料
| 型號(hào)： | IDT54FCT821ADSO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 86K |
| 代理商： | IDT54FCT821ADSO |
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT821/A/B
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
5
NOTES:
1. See test circuit and waveforms.
2. Mnimumlimts are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
IDT54/74FCT821A
Coml.
Mn.
(2)
Max.
—
10
IDT54/74FCT821B
Coml.
Mn.
(2)
Max.
—
7.5
Mil.
Mil.
Parameter Description
t
PLH
t
PHL
Conditions
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
Mn.
(2)
—
Max.
11.5
Mn.
(2)
—
Max.
8.5
Unit
ns
Propagation Delay
CP to Yx (
OE
= LOW)
—
20
—
20
—
15
—
16
t
SU
t
H
t
W
t
PZH
t
PZL
Set-up Time HIGH or LOW, Dx to CP
Hold Time HIGH or LOW, Dx to CP
CP Pulse Width
,
HIGH or LOW
Output Enable Time
OE
to Yx
4
2
7
—
—
—
—
12
4
2
7
—
—
—
—
13
3
—
—
—
8
3
—
—
—
9
1.5
6
—
1.5
6
—
ns
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 5pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
ns
—
23
—
25
—
15
—
16
t
PHZ
t
PLZ
Output Disable Time
OE
to Yx
—
7
—
8
—
6.5
—
7
ns
—
8
—
9
—
7.5
—
8
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT821ADSO | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| IDT74FCT821ALSO | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| IDT74FCT821ALSOB | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| IDT74FCT821BDSO | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| IDT74FCT821BDSOB | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT821BDB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821HATEB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821HCTEB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IDT54FCT845ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT861ADB | 制造商:Integrated Device Technology Inc 功能描述: |
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