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參數(shù)資料
| 型號： | IDT54FCT821BLSO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 86K |
| 代理商： | IDT54FCT821BLSO |
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6
IDT54/74FCT821/A/B
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAV EFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; Z
O
≤
50
; t
F
≤
2.5ns; t
R
≤
2.5ns.
Test
Switch
Open Drain
Disable Low
Enable Low
All Other Tests
Closed
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
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PDF描述 |
|---|---|
| IDT54FCT821BLSOB | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT821HATEB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821HCTEB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IDT54FCT845ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT861ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT861BDB | 制造商:Integrated Device Technology Inc 功能描述: |
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