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參數(shù)資料
| 型號： | IDT54FCT823ADB8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IDT54FCT823ADB8 |
MILITARYANDCOMMERCIAL TEMPERATURERANGES
2
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
PIN CONFIGURATION
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D6
D7
D2
D5
D3
D4
D8
23
22
24
21
17
5
6
7
4
8
D0
VCC
CP
OE
13
14
11
12
D1
GND
CLR
Y6
Y7
Y2
Y5
Y3
Y4
Y8
Y0
Y1
EN
15
16
N
C
12
13
14
G
N
D
8
17
18
C
P
E
N
Y
8
N
C
V
C
O
E
D
1
D
0
Y
0
Y
1
Y3
NC
Y4
5
6
8
7
9
10
11
1
28
43
2
27
26
25
24
22
23
21
20
19
D5
NC
D3
D4
D2
D7
D6
INDEX
Y5
C
L
R
Y2
Y7
Y6
LOGIC SYMBOL
CP
D
OE
Q
D
CP
Y
9
EN
CLR
EN
Symbol
Rating
Commercial
Military
Unit
VTERM(2)
Terminal Voltage
–0.5 to +7
V
with Respect to GND
VTERM(3)
Terminal Voltage
–0.5 to VCC
V
with Respect to GND
TA
Operating Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature under BIAS
–55 to +125
–65 to +135
°C
TSTG
Storage Temperature
–55 to +125
–65 to +150
°C
PT
Power Dissipation
0.5
W
IOUT
DC Output Current
120
mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
Pin Name
I/O
Description
Dx
I
D flip-flop data inputs
CLR
I
For both inverting and non-inverting registers, when
the clear input is LOW and OE is LOW, the Qx
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
C P
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Y x
O
Register 3-state outputs
EN
I
Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the QI output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the QI outputs do not change state,
regardless of the data or clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the OE
input is LOW, the TRUE register data is present at the
Yx outputs.
PIN DESCRIPTION
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