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參數資料
| 型號： | IDT54FCT823CTD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數： | 7/9頁 |
| 文件大小： | 178K |
| 代理商： | IDT54FCT823CTD |
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825CT
FCT823DT
Com'l.
Mil.
Com'l.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
Min
.
(2)
1.5
Max.
6.0
Min
.
(2)
1.5
Max.
7.0
Min
.
(2)
1.5
Max.
5.0
Unit
ns
Propagation Delay
CP to Y
I
(
OE
= LOW)
1.5
12.5
1.5
13.5
1.5
8.5
t
SU
Set-up Time HIGH or LOW
D
I
to CP
Hold Time HIGH or LOW
D
I
to CP
Set-up Time HIGH or LOW
EN
to CP
Hold Time HIGH or LOW
EN
to CP
Propagation Delay,
CLR
to Y
I
3.0
—
3.0
—
2.0
—
ns
t
H
1.5
—
1.5
—
1.0
—
ns
t
SU
3.0
—
3.0
—
3.0
—
ns
t
H
0
—
0
—
0
—
ns
t
PHL
1.5
8.0
1.5
8.5
1.5
5.0
ns
t
REM
Recovery Time
CLR
to CP
6.0
—
6.0
—
3.0
—
ns
t
W
Clock Pulse Width
HIGH or LOW
(3)
CLR
Pulse Width LOW
(3)
6.0
—
6.0
—
3.0
—
ns
t
W
t
PZH
t
PZL
6.0
1.5
—
7.0
6.0
1.5
—
8.0
3.0
1.5
—
4.8
ns
ns
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 5pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
1.5
12.5
1.5
13.5
1.5
9.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
1.5
6.0
1.5
6.0
1.5
4.0
ns
1.5
6.5
1.5
6.5
1.5
4.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
2567 tbl 09
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| IDT54FCT823CTDB | Ceramic Chip Capacitors / Standard X7R; Capacitance [nom]: 4.7uF; Working Voltage (Vdc)[max]: 16V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R; Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
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