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參數(shù)資料
| 型號(hào)： | IDT54FCT824BDB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 中文描述： | FCT SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | IDT54FCT824BDB |
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.19
7
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
Pulse
Generator
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
t
SU
t
H
t
REM
H
t
SU
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OL
V
OH
t
PLH
t
PHL
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
3V
1.5V
0V
t
PLH
t
PHL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
t
NOTES
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0 MHz; Z
O
≤
50
; t
F
≤
2.5ns;
t
R
≤
2.5ns.
2608 drw 01
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2608 tbl 09
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT824BE | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT824BEB | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT824BL | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT824BP | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT824BPB | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
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