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參數(shù)資料
| 型號(hào)： | IDT54FCT825BDB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 中文描述： | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 186K |
| 代理商： | IDT54FCT825BDB |
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.19
3
PRODUCT SELECTOR GUIDE
2608 tbl 01
PIN DESCRIPTION
FUNCTION TABLE
(1)
IDT54/74FCT821/823/825
FUNCTION TABLE
(1)
IDT54/74FCT824
2608 tbl 10
Device
9-Bit
10-Bit
8-Bit
Non-inverting
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
Inverting
54/74FCT824A/B/C
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
↑
= LOW-to-HIGH
Transition, Z = High Impedance
2608 tbl 02
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
↑
= LOW-to-
HIGH Transition, Z = High Impedance
2608 tbl 03
Name
D
I
CLR
I/O
I
I
Description
The D flip-flop data inputs.
For both inverting and non-inverting
registers, when the clear input is LOW
and
OE
is LOW, the Q
I
outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
The register three-state outputs.
Clock Enable. When the clock enable
is LOW, data on the D
transferred to the Q
I
output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the Q
I
outputs
do
not
regardless of the data or clock input
transitions.
Output Control. When the
OE
input is
HIGH, the Y
impedance state. When the
OE
input is
LOW, the TRUE register data is
present at the Y
I
outputs.
CP
I
Y
I ,
Y
I
O
I
EN
input is
change
state,
OE
I
outputs are in the high
Inputs
Internal/
Outputs
Q
I
L
H
L
L
NC
NC
L
H
L
H
OE
CLR
EN
D
I
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Y
I
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
H
H
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
Clear
Hold
Load
Inputs
Internal/
Outputs
Q
I
H
L
L
L
NC
NC
H
L
H
L
OE
CLR
EN
D
I
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Y
I
Z
Z
Z
L
Z
NC
Z
Z
H
L
Function
High Z
H
H
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
Clear
Hold
Load
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