參數(shù)資料
型號(hào): IDT54FCT825CTD
廠商: Integrated Device Technology, Inc.
英文描述: CAP 0.82UF 50V 10% X7R SMD-1210 TR-7-PL SN-NIBAR
中文描述: 高性能CMOS總線接口寄存器
文件頁數(shù): 6/9頁
文件大?。?/td> 178K
代理商: IDT54FCT825CTD
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
6
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT
FCT821/823/825BT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
Min
.
(2)
1.5
Max.
10.0
Min
.
(2)
1.5
Max.
11.5
Min
.
(2)
1.5
Max.
7.5
Min
.
(2)
1.5
Max.
8.5
Unit
ns
Propagation Delay
CP to Y
I
(
OE
= LOW)
1.5
20.0
1.5
20.0
1.5
15.0
1.5
16.0
t
SU
Set-up Time HIGH or LOW
D
I
to CP
Hold Time HIGH or LOW
D
I
to CP
Set-up Time HIGH or LOW
EN
to CP
Hold Time HIGH or LOW
EN
to CP
Propagation Delay,
CLR
to Y
I
4.0
4.0
3.0
3.0
ns
t
H
2.0
2.0
1.5
1.5
ns
t
SU
4.0
4.0
3.0
3.0
ns
t
H
2.0
2.0
0
0
ns
t
PHL
1.5
14.0
1.5
15.0
1.5
9.0
1.5
9.5
ns
t
REM
Recovery Time
CLR
to CP
6.0
7.0
6.0
6.0
ns
t
W
Clock Pulse Width
HIGH or LOW
CLR
Pulse Width LOW
7.0
7.0
6.0
6.0
ns
t
W
t
PZH
t
PZL
6.0
1.5
12.0
7.0
1.5
13.0
6.0
1.5
8.0
6.0
1.5
9.0
ns
ns
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 5pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
1.5
7.0
1.5
8.0
1.5
6.5
1.5
7.0
ns
1.5
8.0
1.5
9.0
1.5
7.5
1.5
8.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
2567 tbl 08
相關(guān)PDF資料
PDF描述
IDT54FCT825CTDB HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
IDT54FCT825CTE HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
IDT54FCT825CTEB HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
IDT54FCT825CTL HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
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